Multiple layers can be utilized in semiconductor fabrication for shrinking design parameters. However, there are challenges in implementing such multiple layer structures. As an example, challenges can arise from the patterning of the layers including, more specifically, dishing from a chemical mechanical polishing (CMP) process. As is understood, dishing may result because of variations in the CMP process, such as a change in tool or change in material properties, amongst other examples.
Certain marks are implemented in each layer to assist in aligning features located in the different layers of the build structure, while other marks are implemented to verify that the alignment is proper. The dishing caused by the CMP process, though, can damage these marks, making alignment and verification of the alignment difficult. As an example, dishing can cause a mark to become thinner in advanced node technologies.
In combination with CMP dishing/erosion, further degradation of the measurement accuracy, along with impacting silicon quality, can occur. These issues become more problematic as the number of layers in the build increases, because the CMP dishing can become more accentuated as the layers accumulate. BEOL can be the most problematic area because of a relatively high hit rate due to the incoming topography accumulations. A similar challenge is also seen in the MOL. As a result, the metrology of the device is impacted.